The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2019

Filed:

Mar. 02, 2010
Applicants:

Thomas Bert Gorczyca, Schenectady, NY (US);

Richard Joseph Saia, Niskayuna, NY (US);

Paul Alan Mcconnelee, Albany, NY (US);

Inventors:

Thomas Bert Gorczyca, Schenectady, NY (US);

Richard Joseph Saia, Niskayuna, NY (US);

Paul Alan McConnelee, Albany, NY (US);

Assignee:

General Electric Company, Schenectady, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/4985 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/3011 (2013.01);
Abstract

A chip package is disclosed that includes an electronic chip having a plurality of die pads formed on a top surface thereof, with a polyimide flex layer positioned thereon by way of an adhesive layer. A plurality of vias is formed through the polyimide flex layer and the adhesive layer corresponding to the die pads. A plurality of metal interconnects are formed on the polyimide flex layer each having a cover pad covering a portion of a top surface of the polyimide flex layer, a sidewall extending down from the cover pad and through the via along a perimeter thereof, and a base connected to the sidewall and forming an electrical connection with a respective die pad. Each of the base and the sidewall is formed to have a thickness that is equal to or greater than a thickness of the adhesive layer.


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