The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2019

Filed:

Jun. 30, 2016
Applicant:

Avago Technologies International Sales Pe. Limited, Singapore, SG;

Inventors:

Sam Ziqun Zhao, Irvine, CA (US);

Rezaur Rahman Khan, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 21/78 (2006.01); H01L 21/56 (2006.01); H01L 21/60 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4853 (2013.01); H01L 21/561 (2013.01); H01L 21/78 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/24 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 24/13 (2013.01); H01L 24/82 (2013.01); H01L 24/96 (2013.01); H01L 2021/60135 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/24011 (2013.01); H01L 2224/24101 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/25171 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/96 (2013.01); H01L 2924/18161 (2013.01);
Abstract

An integrated circuit (IC) package is disclosed that contains high density interconnects to connect multiple dies. The IC package includes an encapsulated layer, a first dielectric layer, and a second dielectric layer. The encapsulated layer forms the base of the IC package and includes the multiple dies. The first dielectric layer positioned between the encapsulated layer and the second layer. The first dielectric layer includes vias to connect to the input/output pads of active surfaces of the multiple dies. The second dielectric layer includes interconnect layers where at least one of the interconnect layers forms an electrical path to connect at least two of the multiple dies together. According to embodiments of the present disclosure, the IC package enables a high manufacturing yield due to large tolerances allowed for selection of dies. Embodiments of the present disclosure also increase an amount of input/output interconnection between multiple dies in the IC package. Embodiments of the present disclosure further enable lower manufacturing costs because of the use of mature reconstituted dies and redistribution layer technologies and the lack of a need for an interposer to connect multiple dies.


Find Patent Forward Citations

Loading…