The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 30, 2019

Filed:

Jul. 20, 2015
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Ya-Ling Lee, Hsinchu, TW;

Lin-Jung Wu, Miaoli, TW;

Victor Y. Lu, Foster City, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 21/288 (2006.01); H01L 21/768 (2006.01); H01L 21/285 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/31111 (2013.01); H01L 21/2885 (2013.01); H01L 21/28556 (2013.01); H01L 21/28568 (2013.01); H01L 21/76802 (2013.01); H01L 21/76856 (2013.01); H01L 21/76873 (2013.01); H01L 21/76879 (2013.01); H01L 23/5329 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H01L 21/76843 (2013.01); H01L 2221/1063 (2013.01);
Abstract

The present disclosure relates to an improved method of forming interconnection layers to reduce voids and improve reliability, and an associated device. In some embodiments, a dielectric layer is formed over a semiconductor substrate having an opening arranged within the dielectric layer. A metal seed layer is formed on the surfaces of the opening using a chemical vapor deposition (CVD) process. Then a metal layer is plated onto the metal seed layer to fill the opening. Forming the metal seed layer using a CVD process provides the seed layer with a good uniformity, which allows for high aspect ratio openings in the dielectric layer to be filled without voids or pinch off.


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