The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 2019
Filed:
Dec. 09, 2016
Applicant:
Microsemi Soc Corporation, San Jose, CA (US);
Inventors:
John L. McCollum, Orem, UT (US);
Esmat Z. Hamdy, Fremont, CA (US);
Assignee:
Microsemi SoC Corporation, San Jose, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); H03K 19/094 (2006.01); H01L 27/24 (2006.01); H01L 23/00 (2006.01); H03K 19/177 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
H03K 19/1776 (2013.01); G11C 13/003 (2013.01); G11C 13/0026 (2013.01); G11C 13/0069 (2013.01); H01L 24/26 (2013.01); H01L 24/36 (2013.01); H01L 27/2436 (2013.01); H01L 27/2454 (2013.01); H01L 27/2463 (2013.01); H01L 45/12 (2013.01); H03K 19/0941 (2013.01); G11C 2213/79 (2013.01);
Abstract
A low-leakage resistive random access memory cell includes a complementary pair of bit lines and a switch node. A first ReRAM device is connected to a first one of the bit lines. A p-channel transistor has a source connected to the ReRAM device, a drain connected to the switch node, and a gate connected to a bias potential. A second ReRAM device is connected to a second one of the bit lines. An n-channel transistor has a source connected to the ReRAM device a drain connected to the switch node, and a gate connected to a bias potential.