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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10269622 B1

PDFFull Text
Date of Patent:
Apr. 23, 2019

Filed:

Dec. 24, 2014

Materials and deposition schemes using photoactive materials for interface chemical control and patterning of predefined structures

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Rami Hourani, Portland, OR (US);

Michael J. Leeson, Portland, OR (US);

Todd R. Younkin, Portland, OR (US);

Eungnak Han, Portland, OR (US);

Robert L. Bristol, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Schwabe, Williamson & Wyatt, P.C.

Primary Examiner:

Marvin Payen

Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); G03F 7/00 (2006.01); G03F 7/16 (2006.01); H01L 21/027 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76816 (2013.01); G03F 7/0035 (2013.01); G03F 7/165 (2013.01); H01L 21/0271 (2013.01); H01L 21/76808 (2013.01); H01L 21/76825 (2013.01); H01L 21/76831 (2013.01); H01L 21/76897 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/5329 (2013.01);
Abstract

Embodiments of the invention include microelectronic devices and methods of forming such devices. In an embodiment, a microelectronic device, includes one or more pre-patterned features formed into a interconnect layer, with a conformal barrier layer formed over the first wall, and the second wall of one or more of the pre-patterned features. A photoresist layer may formed over the barrier layer and within one or more of the pre-patterned features and a conductive via may be formed in at least one of the pre-patterned features.

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