The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 23, 2019
Filed:
Sep. 23, 2016
Sandisk Technologies Llc, Plano, TX (US);
Jixin Yu, Milpitas, CA (US);
Zhenyu Lu, Milpitas, CA (US);
Hiroyuki Ogawa, Yokkaichi, JP;
Daxin Mao, Cupertino, CA (US);
Kensuke Yamaguchi, Yokkaichi, JP;
Sung Tae Lee, Yokkaichi, JP;
Yao-sheng Lee, Tampa, FL (US);
Johann Alsmeier, San Jose, CA (US);
SANDISK TECHNOLOGIES LLC, Addison, TX (US);
Abstract
Contacts to peripheral devices extending through multiple tier structures of a three-dimensional memory device can be formed with minimal additional processing steps. First peripheral via cavities through a first tier structure can be formed concurrently with formation of first memory openings. Sacrificial via fill structures can be formed in the first peripheral via cavities concurrently with formation of sacrificial memory opening fill structures that are formed in the first memory openings. Second peripheral via cavities through a second tier structure can be formed concurrently with formation of word line contact via cavities that extend to top surfaces of electrically conductive layers in the first and second tier structures. After removal of the sacrificial via fill structures, the first and second peripheral via cavities can be filled with a conductive material to form peripheral contact via structures concurrently with formation of word line contact via structures.