The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 23, 2019

Filed:

Mar. 22, 2018
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Wen-Yi Lin, New Taipei, TW;

Po-Yao Lin, Hsinchu County, TW;

Shin-Puu Jeng, Hsinchu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/67 (2006.01); G01N 21/95 (2006.01); G01B 11/16 (2006.01); G01B 11/24 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67288 (2013.01); G01B 11/16 (2013.01); G01B 11/24 (2013.01); G01N 21/9501 (2013.01); H01L 21/67103 (2013.01); G01N 2201/0231 (2013.01);
Abstract

The present disclosure provides a system for wafer warpage inspection including a heatable susceptor configured to heat a wafer according to a predetermined temperature profile. The system for wafer warpage inspection further includes a confocal imager array over the heatable susceptor configured to capture one or more warpage parameters of the wafer. Each confocal imager of the confocal imager array covers a predetermined field of view (FOV). The system for wafer warpage inspection further includes a first actuator permitting the confocal imager array to move in a plurality of directions. The system for wafer warpage inspection further includes a processing unit connected to the confocal imager array. The processing unit is configured to dynamically process the one or more warpage parameters captured during the heating of the wafer according to the predetermined temperature profile. Present disclosure also provides a method for wafer warpage inspection described herein.


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