The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2019

Filed:

Nov. 30, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Hui Zang, Guilderland, NY (US);

Ruilong Xie, Niskayuna, NY (US);

Tek Po Rinus Lee, Ballston Spa, NY (US);

Lars Liebmann, Mechanicville, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Caymay, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 21/336 (2006.01); H01L 21/8238 (2006.01); H01L 29/808 (2006.01); H01L 29/788 (2006.01); H01L 27/088 (2006.01); H01L 21/302 (2006.01); H01L 27/092 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
H01L 29/8083 (2013.01); H01L 21/302 (2013.01); H01L 21/3065 (2013.01); H01L 21/8234 (2013.01); H01L 21/8238 (2013.01); H01L 27/088 (2013.01); H01L 27/092 (2013.01); H01L 29/78 (2013.01); H01L 29/786 (2013.01); H01L 29/7889 (2013.01);
Abstract

A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor including a gate contact patterned in a self-aligned process. In one embodiment, we disclose a semiconductor device, including a semiconductor substrate and a first vertical field effect transistor (vFET) including a bottom source/drain (S/D) region disposed on the semiconductor substrate; a fin disposed above the bottom S/D region; a top source/drain (S/D) region disposed above the fin and having a top surface; and a gate having a top surface higher than the top surface of the top S/D region. A gate contact may be formed over the gate.


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