The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 16, 2019
Filed:
Jun. 26, 2018
Applicant:
Nephos (Hefei) Co. Ltd., Hefei, Anhui, CN;
Inventors:
Yi-Hung Chen, Yilan County, TW;
Yuan-Chin Liu, Hsinchu, TW;
Assignee:
Nephos (Hefei) Co. Ltd., Hefei, Anhui, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/362 (2006.01); G06F 13/40 (2006.01); H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
G06F 13/362 (2013.01); G06F 13/4022 (2013.01); H04L 7/00 (2013.01); H04L 7/005 (2013.01); H04L 7/0008 (2013.01);
Abstract
A wafer-level package includes a first die and a second die that are wafer-level packaged. The first die has a first clock source. The second die has a second clock source. The first clock source generates a clock shared by the first die and the second die. The second clock source, however, does not generate a clock used by any of the first die and the second die.