The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 16, 2019
Filed:
Sep. 25, 2015
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Zhe Wang, Hillsboro, OR (US);
Christopher B. Wilkerson, Portland, OR (US);
Zeshan A. Chishti, Hillsboro, OR (US);
Seth H. Pugsley, Salt Lake City, UT (US);
Alaa R. Alameldeen, Hillsboro, OR (US);
Shih-Lien L. Lu, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/0811 (2016.01); G06F 3/06 (2006.01); G06F 12/0862 (2016.01); G06F 12/0888 (2016.01); G06F 12/0893 (2016.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0811 (2013.01); G06F 3/065 (2013.01); G06F 3/0619 (2013.01); G06F 3/0685 (2013.01); G06F 12/0862 (2013.01); G06F 12/0888 (2013.01); G06F 12/0893 (2013.01); G06F 2212/283 (2013.01); G06F 2212/6026 (2013.01); G06F 2212/7202 (2013.01);
Abstract
An apparatus is described. The apparatus includes a last level cache and a memory controller to interface to a multi-level system memory. The multi-level system memory has a caching level. The apparatus includes a first prediction unit to predict unneeded blocks in the last level cache. The apparatus includes a second prediction unit to predict unneeded blocks in the caching level of the multi-level system memory.