The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2019

Filed:

Jan. 14, 2018
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Yu-Hsiang Hung, Tainan, TW;

Ssu-I Fu, Kaohsiung, TW;

Chao-Hung Lin, Changhua County, TW;

Chih-Kai Hsu, Tainan, TW;

Jyh-Shyang Jenq, Pingtung County, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 23/535 (2006.01); H01L 27/11 (2006.01); H01L 21/768 (2006.01); H01L 21/033 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/0332 (2013.01); H01L 21/0335 (2013.01); H01L 21/0337 (2013.01); H01L 21/0338 (2013.01); H01L 21/76816 (2013.01); H01L 21/76895 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823475 (2013.01); H01L 21/823481 (2013.01); H01L 23/535 (2013.01); H01L 27/1104 (2013.01); H01L 27/1116 (2013.01); H01L 28/00 (2013.01); H01L 29/0653 (2013.01); H01L 29/0847 (2013.01); H01L 29/66545 (2013.01); H01L 29/7851 (2013.01);
Abstract

A semiconductor device and method of forming the same, the semiconductor device includes a first and second fin shaped structures, a first and second gate structures and a first and second plugs. The first and second fin shaped structures are disposed on a first region and a second region of a substrate and the first and second gate structure are disposed across the first and second fin shaped structures, respectively. A dielectric layer is disposed on the substrate, covering the first and second gate structure. The first and second plugs are disposed in the dielectric layer, wherein the first plug is electrically connected first source/drain regions adjacent to the first gate structure and contacts sidewalls of the first gate structure, and the second plug is electrically connected to second source/drain regions adjacent to the second gate structure and not contacting sidewalls of the second gate structure.


Find Patent Forward Citations

Loading…