The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10256140 B1

Date of Patent:

Apr. 09, 2019

Filed:

Oct. 19, 2017

Method of reducing overlay error in via to grid patterning

Applicant:

Tokyo Electron Limited, Minato-ku, Tokyo, JP;

Inventor:

Nihar Mohanty, Clifton Park, NY (US);

Assignee:

Tokyo Electron Limited, Tokyo, JP;

Attorney:

Primary Examiner:

Duy Vu N Deo

Int. Cl.

CPC ...

H01L 21/768 (2006.01); H01L 21/033 (2006.01); H01L 21/311 (2006.01); H01L 23/535 (2006.01);

U.S. Cl.

CPC ...

H01L 21/76816 (2013.01); H01L 21/0332 (2013.01); H01L 21/0337 (2013.01); H01L 21/31144 (2013.01); H01L 21/76897 (2013.01); H01L 23/535 (2013.01);

Abstract

Techniques herein include a method of patterning a substrate that uses a self-alignment based process to align a via to odd and even trenches by using multiple different materials. Methods herein decompose or separate a via pattern into spacer side via and mandrel side via, and then sequentially access the spacer side and mandrel side respectively. With such a technique, overlay of via to grid is significantly improved. By using an additional memorization layer underneath a trench memorization layer and independently accessing the spacer side and mandrel side in the midst of a trench pattern, significant improvement in via alignment is achieved.

Find Patent Forward Citations