The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 09, 2019
Filed:
Nov. 03, 2017
Cypress Semiconductor Corporation, San Jose, CA (US);
Ching-Huang Lu, Fremont, CA (US);
Lei Xue, Saratoga, CA (US);
Kenichi Ohtsuka, Sunnyvale, CA (US);
Simon Siu-Sing Chan, Saratoga, CA (US);
Rinji Sugino, San Jose, CA (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
An A method for fabricating an integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate is described herein. The trench is self-aligned between the first and second devices and comprises a first portion filled with a dielectric material and a second portion filled with a conductive material. The self-aligned placement of the trench provides electrical isolation between the first and second devices and allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.