The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2019

Filed:

Mar. 28, 2018
Applicant:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Remi Coquand, Les Marches, FR;

Emmanuel Augendre, Montbonnot, FR;

Shay Reboh, Grenoble, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/285 (2006.01); H01L 29/66 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/775 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 21/02 (2006.01); H01L 29/45 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28518 (2013.01); H01L 21/02532 (2013.01); H01L 21/02603 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/401 (2013.01); H01L 29/41725 (2013.01); H01L 29/42392 (2013.01); H01L 29/458 (2013.01); H01L 29/66439 (2013.01); H01L 29/66742 (2013.01); H01L 29/775 (2013.01); H01L 29/78651 (2013.01); H01L 29/78696 (2013.01);
Abstract

A process for fabricating a gate-wrap-around field-effect transistor is provided, including providing a substrate surmounted with first and second nanowires extending in a same longitudinal direction and having a median portion covered by a first material, and first and second ends that are arranged on either side of the median portion, a periphery of which is covered by respective first and second dielectric spacers made of a second material that is different from the first material, the ends having exposed lateral faces; doping a portion of the first and second ends via the lateral faces; depositing an amorphous silicon alloy on the first and second lateral faces followed by crystallizing the alloy; and depositing a metal on either side of the nanowires to form first and second metal contacts that respectively make electrical contact with the doped portions of the first and second ends of the nanowires.


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