The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2019

Filed:

Feb. 26, 2018
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Tsung-Mu Lai, Hsinchu County, TW;

Wen-Hao Ching, Hsinchu County, TW;

Chen-Hao Po, Hsinchu, TW;

Assignee:

eMemory Technology Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/30 (2006.01); G11C 16/12 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); H01L 27/11558 (2017.01); G11C 16/10 (2006.01); G11C 16/16 (2006.01); H01L 27/11521 (2017.01); H01L 27/11526 (2017.01); G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 7/22 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); H01L 23/528 (2006.01); H01L 27/02 (2006.01); H01L 27/11517 (2017.01); G11C 7/06 (2006.01); G11C 8/10 (2006.01); H01L 27/11524 (2017.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 27/11519 (2017.01);
U.S. Cl.
CPC ...
G11C 16/30 (2013.01); G11C 7/065 (2013.01); G11C 7/10 (2013.01); G11C 7/12 (2013.01); G11C 7/22 (2013.01); G11C 8/10 (2013.01); G11C 16/0408 (2013.01); G11C 16/0433 (2013.01); G11C 16/0458 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/12 (2013.01); G11C 16/14 (2013.01); G11C 16/16 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); H01L 23/528 (2013.01); H01L 27/0207 (2013.01); H01L 27/11517 (2013.01); H01L 27/11519 (2013.01); H01L 27/11521 (2013.01); H01L 27/11524 (2013.01); H01L 27/11526 (2013.01); H01L 27/11558 (2013.01); H01L 27/1203 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/1095 (2013.01); H01L 29/42328 (2013.01);
Abstract

A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. The floating gate module is disposed in a first well, the erase element is disposed in a second well, and the control element is disposed in a third well. The first well, the second well and the third well are disposed in a deep doped region, and memory cells of the plurality of memory pages are all disposed in the deep doped region. Therefore, the spacing rule between deep doped regions is no longer be used to limit the circuit area of the memory array and the circuit area of the memory array can be reduced.


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