The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 09, 2019

Filed:

Oct. 31, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Krishnan Srinivasan, San Jose, CA (US);

Robert P. Adler, Santa Clara, CA (US);

Eric A. Geisler, Hillsboro, OR (US);

Robert De Gruijl, San Francisco, CA (US);

Jay Tomlinson, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); H04L 29/12 (2006.01);
U.S. Cl.
CPC ...
G06F 17/505 (2013.01); G06F 13/4068 (2013.01); G06F 13/4282 (2013.01); H04L 61/2007 (2013.01); G06F 2213/0026 (2013.01);
Abstract

In one embodiment, a design tool for designing a system on chip (SoC) includes hardware mapping logic to automatically generate a channel mapping for a path between a first intellectual property (IP) logic of the SoC and a second IP logic of the SoC. The hardware mapping logic, based at least in part on user input of a source channel associated with the first IP logic, a sink channel associated with the second IP logic and at least one derivation parameter, is to generate the channel mapping according to one of a plurality of derivation algorithms. Other embodiments are described and claimed.


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