The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2019

Filed:

Aug. 20, 2017
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chiu-Jung Chiu, Tainan, TW;

Hung-Chan Lin, Tainan, TW;

Yu-Chun Chen, Kaohsiung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 27/06 (2006.01); H01L 21/768 (2006.01); H01L 29/94 (2006.01); H01L 49/02 (2006.01); H01L 21/8234 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76237 (2013.01); H01L 21/02197 (2013.01); H01L 21/28202 (2013.01); H01L 21/76822 (2013.01); H01L 21/8234 (2013.01); H01L 27/0629 (2013.01); H01L 28/92 (2013.01); H01L 29/94 (2013.01);
Abstract

An integrated circuit includes a first insulation layer, a bottom plate, a first patterned dielectric layer, a medium plate, a second patterned dielectric layer, and a top plate. The first patterned dielectric layer is disposed on the bottom plate. The medium plate is disposed on the first patterned dielectric layer. At least a part of the first patterned dielectric layer and the medium plate and a part of the bottom plate are disposed in a first trench penetrating the first insulation layer. The bottom plate, the first patterned dielectric layer, and the medium plate constitute a first metal-insulator-metal (MIM) capacitor. The second patterned dielectric layer is disposed on the medium plate. The top plate is disposed on the second patterned dielectric layer. The medium plate, the second patterned dielectric layer, and the top plate constitute a second MIM capacitor. The bottom plate is electrically connected with the top plate.


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