The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 02, 2019

Filed:

Jun. 26, 2018
Applicant:

Stmicroelectronics International N.v., Schiphol, NL;

Inventors:

Harsh Rawat, Haryana, IN;

Abhishek Pathak, Nowgong, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G11C 7/06 (2006.01); G11C 11/419 (2006.01); G11C 11/418 (2006.01); G06F 1/06 (2006.01); G06F 13/16 (2006.01); G11C 7/10 (2006.01); G11C 8/16 (2006.01); G11C 11/413 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G06F 1/06 (2013.01); G06F 13/1689 (2013.01); G11C 7/1075 (2013.01); G11C 8/16 (2013.01); G11C 11/413 (2013.01); G11C 11/418 (2013.01);
Abstract

A memory array has word lines and bit lines. A row decoder is operable to decode a row address and select a corresponding word line. A read-write clock generator is operable to generate a hold clock signal. An address clock generator receives a read address, a write address, a dual port mode control signal, a read chip select signal, and a write chip select signal. When operating in dual port mode, and when operating in a read mode, the address clock generator applies a read delay to the read address and outputs the read address, as delayed, to the row pre-decoder as the address in response to the hold clock signal.


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