The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2019

Filed:

Sep. 23, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kevin J. Fischer, Hillsboro, OR (US);

Christopher M. Pelto, Beaverton, OR (US);

Andrew W. Yeoh, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); H01L 21/76852 (2013.01); H01L 21/76879 (2013.01); H01L 21/76885 (2013.01); H01L 23/522 (2013.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H01L 23/5329 (2013.01); H01L 2924/0002 (2013.01);
Abstract

An embodiment includes a semiconductor structure comprising: a frontend portion including a device layer; a backend portion including a bottom metal layer, a top metal layer, and intermediate metal layers between the bottom and top metal layers; wherein (a) the top metal layer includes a first thickness that is orthogonal to the horizontal plane in which the top metal layer lies, the bottom metal layer includes a second thickness; and the intermediate metal layers includes a third thickness; and (b) the first thickness is greater than or equal to a sum of the second and third thicknesses. Other embodiments are described herein.


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