The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 12, 2019

Filed:

Dec. 14, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

John R. Sporre, Albany, NY (US);

Siva Kanakasabapathy, Pleasanton, CA (US);

Andrew M. Greene, Albany, NY (US);

Jeffrey Shearer, Albany, NY (US);

Nicole A. Saulnier, Albany, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 25/065 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 21/82345 (2013.01); H01L 21/02019 (2013.01); H01L 21/823462 (2013.01); H01L 21/823828 (2013.01); H01L 21/823842 (2013.01); H01L 25/0657 (2013.01); H01L 27/0886 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7831 (2013.01);
Abstract

Semiconductor devices and methods of forming the same include forming dummy gates over a semiconductor fin. An interlayer dielectric is formed around and between the dummy gates. The dummy gates are etched away, leaving gate voids. A first planarizing material is deposited in and over the gate voids. The first planarizing material is removed in a gate cut region. A gate cut plug is deposited in the gate cut region. The remaining first planarizing material is removed to expose the gate voids outside of the gate cut region. A gate stack is formed in the gate voids outside of the gate cut region.


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