The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2019

Filed:

Aug. 30, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Richard A. Conti, Katonah, NY (US);

Jessica Dechene, Albany, NY (US);

Susan S. Fan, Cohoes, NY (US);

Son V. Nguyen, Schenectady, NY (US);

Jeffrey C. Shearer, Albany, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 27/088 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76843 (2013.01); H01L 21/7682 (2013.01); H01L 21/76807 (2013.01); H01L 21/76877 (2013.01); H01L 23/5222 (2013.01); H01L 23/53295 (2013.01); H01L 27/088 (2013.01);
Abstract

An upper layer is formed in a first interlayer dielectric (ILD) layer. The upper layer comprises a plurality of metal interconnects and one or more upper layer air gaps positioned between adjacent metal interconnects. A lower layer is formed in the first ILD layer. The lower layer comprises one or more vias, and one or more lower air gaps positioned between adjacent vias. The upper layer and the lower layer are formed in accordance with a dual-damascene process.


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