The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2019

Filed:

Nov. 15, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Samuel S. Choi, Fishkill, NY (US);

Ronald G. Filippi, Wappingers Falls, NY (US);

Elbert E. Huang, Carmel, NY (US);

Naftali E. Lustig, Croton on Hudson, NY (US);

Griselda Bonilla, Hopewell Junction, NY (US);

Andrew H. Simon, Fishkill, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 23/528 (2006.01); H01L 21/02 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/7682 (2013.01); H01L 21/0217 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 23/528 (2013.01); H01L 23/5329 (2013.01);
Abstract

A method of forming an air gap for a semiconductor device and the device formed are disclosed. The method may include forming an air gap mask layer over a dielectric interconnect layer, the dielectric interconnect layer including a dielectric layer having a conductive interconnect therein and a cap layer over the dielectric layer; patterning the air gap mask layer using extreme ultraviolet (EUV) light and etching to form an air gap mask including an opening in the cap layer exposing a portion of the dielectric layer of the dielectric interconnect layer adjacent to the conductive interconnect; removing the air gap mask; etching an air gap space adjacent to the conductive interconnect within the dielectric layer of the dielectric interconnect layer using the opening in the cap layer; and forming an air gap in the dielectric interconnect layer by depositing an air gap capping layer to seal the air gap space.


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