The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2019

Filed:

Mar. 01, 2018
Applicant:

Stmicroelectronics International N.v., Schiphol, NL;

Inventors:

Ashish Kumar, Ranchi, IN;

Vinay Kumar, Aligarh, IN;

Kedar Janardan Dhori, Ghaziabad, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/419 (2006.01); G11C 11/418 (2006.01); G11C 5/14 (2006.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 5/147 (2013.01); G11C 11/418 (2013.01); G11C 5/063 (2013.01); G11C 5/145 (2013.01);
Abstract

Read stability of a memory is enhanced in low voltage operation mode by selectively boosting a cell supply voltage for a row of memory cells. The boosted voltage results from a capacitive coupling to the word line in that row. The capacitive coupling is implemented by running the metal line of the power supply line for the cell supply voltage and the metal line for the word line adjacent to each other in a common metallization level. The selective voltage boost is controlled in response to operation of a modified memory cell exhibiting a deteriorated write margin. An output of the modified memory cell is compared to a threshold to generate a signal for controlling the selective voltage boost. Word line under-voltage circuitry is further provided to control application of an under-voltage to the word line.


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