The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2019

Filed:

Jan. 06, 2017
Applicant:

Mentor Graphics Corporation, Wilsonville, OR (US);

Inventors:

Xijiang Lin, West Linn, OR (US);

Wu-Tung Cheng, Lake Oswego, OR (US);

Janusz Rajski, West Linn, OR (US);

Assignee:

Mentor Graphics Corporation, Wilsonville, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 3/00 (2006.01); G06F 17/50 (2006.01); G01R 31/3183 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318371 (2013.01); G01R 31/318364 (2013.01); G01R 31/318307 (2013.01); G06F 17/5022 (2013.01); G06F 17/5027 (2013.01); G06F 17/5045 (2013.01); G06F 17/5059 (2013.01);
Abstract

Aspects of the disclosed technology relate to techniques of test pattern generation based on the cell transition fault model. An assignment for two consecutive clock cycles at inputs of a complex cell in a circuit design is determined based on a gate-level representation of the circuit design. The assignment includes a first transition at one of the inputs which is sensitized by remaining part of the assignment to cause a second transition at an output of the complex cell. A test pattern that generates the assignment at the inputs and propagates a value at the output corresponding to the second clock cycle of the two consecutive clock cycles from the output to an observation point is then derived based on the gate-level representation.


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