The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10219390 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 26, 2019

Filed:

Sep. 14, 2015
Applicant:

Unimicron Technology Corp., Taoyuan, TW;

Inventors:

Shih-Pin Hsu, Taoyuan, TW;

Zhao-Chong Zeng, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 3/32 (2006.01); H05K 1/18 (2006.01); H05K 3/46 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H05K 3/32 (2013.01); H01L 23/49822 (2013.01); H05K 1/186 (2013.01); H05K 3/4644 (2013.01); H05K 3/4682 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/00013 (2013.01); H05K 2201/0195 (2013.01); H05K 2201/10015 (2013.01); H05K 2201/10636 (2013.01); Y02P 70/611 (2015.11); Y10T 29/4913 (2015.01);
Abstract

A carrier board having two opposite surfaces is provided and a releasing film and a metal layer are formed on the two opposite surfaces respectively. Each metal layer formed with positioning pads is covered with a first hot-melt-dielectric layer where a passive component is disposed. The passive component has upper and lower surfaces each having electrode pads. Each first hot-melt-dielectric layer is disposed on a core board having a cavity to receive the passive component. A second hot-melt-dielectric layer is stacked on each core board. The first and second hot-melt-dielectric layers are heat pressed to form two dielectric layer units each having a top surface and a bottom surface. The carrier board and the releasing films are removed to separate the dielectric layer units. Wiring layers are formed on each top surface and each bottom surface and electrically connected to the electrode pads of the upper and lower surfaces respectively.


Find Patent Forward Citations

Hsu, Shih-Pin. (2019). Fabrication method of packaging substrate having embedded passive component (U.S. Patent No. 10219390). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10219390

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