The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2019

Filed:

Oct. 16, 2017
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Ming Zhu, Singapore, SG;

Shi Ya Phyllis Lim, Singapore, SG;

Pinghui Li, Singapore, SG;

Yiang Aun Nga, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7824 (2013.01); H01L 29/0653 (2013.01); H01L 29/1087 (2013.01); H01L 29/66689 (2013.01); H01L 29/0869 (2013.01); H01L 29/0886 (2013.01); H01L 29/165 (2013.01); H01L 29/66507 (2013.01);
Abstract

LDMOS transistor structures and integrated circuits including LDMOS transistor structures are provided. An exemplary integrated circuit including an LDMOS transistor structure includes a substrate including a first region and a second region. The substrate includes a bulk layer and, in the second region, an insulator layer overlying the bulk layer and a semiconductor layer overlying the insulator layer. The integrated circuit further includes a gate structure overlying the semiconductor layer. A channel region is formed in the semiconductor layer under the gate structure. The integrated circuit also includes a well contact region on the bulk layer in the first region, a source region overlying the substrate, and a drain region overlying the substrate. A drift region is located between the drain region and the gate structure.


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