The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2019

Filed:

Dec. 24, 2008
Applicants:

Tatiana Shpeisman, Menlo Park, CA (US);

Ali-reza Adl-tabatabai, San Jose, CA (US);

Vijay Menon, Seattle, WA (US);

Inventors:

Tatiana Shpeisman, Menlo Park, CA (US);

Ali-Reza Adl-Tabatabai, San Jose, CA (US);

Vijay Menon, Seattle, WA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01);
U.S. Cl.
CPC ...
G06F 9/466 (2013.01);
Abstract

A method and apparatus for optimizing quiescence in a transactional memory system is herein described. Non-ordering transactions, such as read-only transactions, transactions that do not access non-transactional data, and write-buffering hardware transactions, are identified. Quiescence in weak atomicity software transactional memory (STM) systems is optimized through selective application of quiescence. As a result, transactions may be decoupled from dependency on quiescing/waiting on previous non-ordering transaction to increase parallelization and reduce inefficiency based on serialization of transactions.


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