The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 05, 2019

Filed:

Jul. 18, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Alexander Reznicek, Troy, NY (US);

Dominic J. Schepis, Wappinger Falls, NY (US);

Kangguo Cheng, Schenectady, NY (US);

Bruce B. Doris, Brewster, NY (US);

Pouya Hashemi, White Plains, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/31 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/165 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02647 (2013.01); H01L 21/0237 (2013.01); H01L 21/0243 (2013.01); H01L 21/0245 (2013.01); H01L 21/02532 (2013.01); H01L 21/02538 (2013.01); H01L 21/02639 (2013.01); H01L 21/31 (2013.01); H01L 21/311 (2013.01); H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 27/0924 (2013.01); H01L 29/0649 (2013.01); H01L 29/0657 (2013.01); H01L 29/1054 (2013.01); H01L 29/165 (2013.01); H01L 29/66446 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

One aspect of the disclosure relates to a method of forming a semiconductor structure. The method may include: forming a set of openings within a substrate; forming an insulator layer within each opening in the set of openings; recessing the substrate between adjacent openings containing the insulator layer in the set of openings to form a set of insulator pillars on the substrate; forming sigma cavities within the recessed substrate between adjacent insulator pillars in the set of insulator pillars; and filling the sigma cavities with a semiconductor material over the recessed substrate between adjacent insulator pillars.


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