The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 05, 2019

Filed:

Mar. 21, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Wei Chen, Portland, OR (US);

Rajat Agarwal, Beaverton, OR (US);

Jing Ling, Milpitas, CA (US);

Daniel W. Liu, San Rafael, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/06 (2006.01); G06F 12/08 (2016.01); G06F 3/06 (2006.01); G06F 12/0808 (2016.01); G06F 12/0811 (2016.01); G06F 12/128 (2016.01); G06F 12/0868 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0808 (2013.01); G06F 1/3287 (2013.01); G06F 3/0685 (2013.01); G06F 12/0638 (2013.01); G06F 12/0811 (2013.01); G06F 12/0868 (2013.01); G06F 12/128 (2013.01); G06F 2212/205 (2013.01); G06F 2212/283 (2013.01); G06F 2212/621 (2013.01); G06F 2212/69 (2013.01);
Abstract

Provided are an apparatus, system, and method to flush modified data from a first memory to a persistent second memory. A first memory controller coupled to the first memory includes at least one RAS controller to read a range of addresses in the first memory. In response to receiving a command from the power control unit, the at least one RAS controller is invoked to read data from at least one range of addresses specified for the RAS controller from the first memory. A second memory controller transfers data read from the first memory determined to be modified to the second memory. The first memory controller sends a signal to the power control unit to indicate that the modified data in the range of addresses specified for the RAS controller was flushed to the second memory in response to the RAS controller completing reading the range of addresses.


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