The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 29, 2019

Filed:

Jan. 08, 2018
Applicant:

Spin Transfer Technologies, Fremont, CA (US);

Inventors:

Gian Sharma, Fremont, CA (US);

Amitay Levi, Cupertino, CA (US);

Kuk-Hwan Kim, San Jose, CA (US);

Assignee:

SPIN TRANSFER TECHNOLOGIES, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/49 (2006.01); H01L 29/423 (2006.01); H01L 27/22 (2006.01); H01L 43/08 (2006.01); H01L 27/24 (2006.01); H01L 29/786 (2006.01); G11C 11/412 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7831 (2013.01); H01L 27/228 (2013.01); H01L 29/42392 (2013.01); H01L 29/495 (2013.01); H01L 29/4916 (2013.01); H01L 29/7827 (2013.01); H01L 43/08 (2013.01); G11C 11/412 (2013.01); H01L 21/82345 (2013.01); H01L 27/2472 (2013.01); H01L 29/78642 (2013.01);
Abstract

A device having two transistors with dual thresholds, and a method of fabricating the device, including fabricating a silicide source, a conductive layer, and contacts to a plurality of layers of the device, is provided. The device has a core and a plurality of layers that surround the core in succession, including a first layer, a second layer, a third layer, and a fourth layer. The device further comprises a first input terminal coupled to the core, the first input terminal being configured to receive a first voltage and a second input terminal coupled to the fourth layer, the second input terminal being configured to receive a second voltage. The device comprises a common source terminal coupled to the core and the fourth layer. A memory device, such as an MTJ, may be coupled to the device.


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