The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 29, 2019

Filed:

Jul. 31, 2017
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Purakh Raj Verma, Singapore, SG;

Shaoqiang Zhang, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/16 (2006.01); H01L 29/20 (2006.01); H01L 21/84 (2006.01); H01L 21/82 (2006.01); H01L 21/8252 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1207 (2013.01); H01L 21/8213 (2013.01); H01L 21/8252 (2013.01); H01L 21/84 (2013.01); H01L 29/1608 (2013.01); H01L 29/20 (2013.01); H01L 29/2003 (2013.01);
Abstract

Devices and methods for forming a device are presented. The method for forming the device includes providing a support substrate having first crystal orientation. A trap rich layer is formed on the support substrate. An insulator layer is formed over a top surface of the trap rich layer. The method further includes forming a top surface layer having second crystal orientation on the insulator layer. The support substrate, the trap rich layer, the insulator layer and the top surface layer correspond to a substrate and the substrate is defined with at least first and second device regions. A transistor is formed in the top surface layer in the first device region and a wide band gap device is formed in the second device region.


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