The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 29, 2019
Filed:
Apr. 17, 2018
Cypress Semiconductor Corporation, San Jose, CA (US);
Chun Chen, San Jose, CA (US);
Yoram Betser, Mazkeret Batya, IL;
Kuo Tung Chang, Saratoga, CA (US);
Amichai Givant, Rosh Ha'Ayin, IL;
Shivananda Shetty, San Jose, CA (US);
Shenqing Fang, Sunnyvale, CA (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with one another, and the first and second source regions may not be electrically coupled with one another. Each of the first and second source regions may be electrically coupled with at least another source region of the same column in the memory array.