The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 22, 2019

Filed:

Jan. 08, 2018
Applicant:

Spin Transfer Technologies, Inc., Fremont, CA (US);

Inventors:

Kuk-Hwan Kim, San Jose, CA (US);

Dafna Beery, Palo Alto, CA (US);

Gian Sharma, Fremont, CA (US);

Amitay Levi, Cupertino, CA (US);

Andrew J. Walker, Mountain View, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/22 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 29/49 (2006.01); H01L 43/08 (2006.01); H01L 43/12 (2006.01); H01L 29/45 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 27/228 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01); H01L 43/08 (2013.01); H01L 43/12 (2013.01); H01L 29/42392 (2013.01); H01L 29/45 (2013.01); H01L 29/495 (2013.01); H01L 29/4916 (2013.01); H01L 29/4966 (2013.01); H01L 29/51 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01); H01L 29/7831 (2013.01); H01L 29/78642 (2013.01);
Abstract

In one embodiment, an apparatus includes lower electrodes positioned below a surface of a substrate, the substrate including crystalline Si, a plurality of strap regions positioned above the lower electrodes and below sets of pillars of Si, the pillars rising above the substrate, the sets of pillars being aligned in a first direction along a plane perpendicular to a film thickness direction, and the strap regions extending above a surface of the substrate, silicide junctions positioned between each of the strap regions and a corresponding lower electrode positioned therebelow, upper electrodes positioned above each of the pillars, gate dielectric layers positioned on sides of the pillars to a height greater than a lower edge of the upper electrodes, and gate layers positioned on sides of the gate dielectric layers in a second direction along the plane and perpendicular to the first direction that transverse a plurality of sets of pillars.


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