The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 15, 2019

Filed:

Apr. 29, 2016
Applicant:

Adesto Technologies Corporation, Sunnyvale, CA (US);

Inventors:

Ming Sang Kwan, San Leandro, CA (US);

Venkatesh P. Gopinath, Fremont, CA (US);

Assignee:

Adesto Technologies Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/249 (2013.01); G11C 13/0011 (2013.01); G11C 13/0069 (2013.01); H01L 27/2436 (2013.01); H01L 45/085 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01);
Abstract

A memory device can include at least one plate structure formed over a semiconductor substrate; an active region formed within the semiconductor substrate without lateral isolation structures; a plurality of bit line contact groups, each including bit line contacts to the active region disposed in a first direction; a plurality of storage contact groups, each including storage contacts to the active region disposed in the first direction; a plurality of gate structures, each including a main section extending in the first direction, and disposed between one bit line contact group and an adjacent storage contact group; and a two-terminal storage element disposed between each bit line contact and the at least one plate structure.


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