The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 15, 2019

Filed:

Jul. 17, 2017
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chan-Yu Hung, Tainan, TW;

Ling-Sung Wang, Tainan, TW;

Yu-Jen Chen, Tainan, TW;

I-Shan Huang, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 27/02 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 21/3065 (2006.01); H01L 21/027 (2006.01); H01L 21/308 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823456 (2013.01); H01L 21/823431 (2013.01); H01L 27/0207 (2013.01); H01L 27/0886 (2013.01); H01L 29/42376 (2013.01); H01L 29/4958 (2013.01); H01L 29/4966 (2013.01); H01L 21/0274 (2013.01); H01L 21/3065 (2013.01); H01L 21/3081 (2013.01);
Abstract

Semiconductor device structures with reduced gate end width formed at gate structures and methods for manufacturing the same are provided. In one example, a semiconductor device structure includes a plurality of gate structures formed over a plurality of fin structures, the gate structures formed substantially orthogonal to the fin structures, wherein the plurality of gate structures includes a first gate structure having a first gate end width and a second gate structure having a second gate end width, wherein the second gate end width is shorter than the first gate end width.


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