Method for fabricating merging semiconductor integrated circuit

Abstract

A method for fabricating a semiconductor integrated circuit (IC) having a SONOS memory device and a logic/analog device requiring different gate oxide layers comprises steps as follows: A substrate having a high voltage region, a memory region and a logic/analog is firstly provided. Next, a first gate oxide layer is formed on the high voltage region, the memory region and the logic/analog. The first gate oxide layer is then patterned to expose the logic/analog region and to define a first channel area and a second channel area respectively on the memory region and the high voltage region. Subsequently, a silicon oxide-silicon nitride-silicon oxide (ONO) structure is formed on the first channel area. A second gate oxide layer is then formed on the logic/analog and patterned to define a third channel area.