The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 08, 2019

Filed:

Nov. 30, 2016
Applicant:

Qorvo Us, Inc., Greensboro, NC (US);

Inventors:

Kevin J. Anderson, Plano, TX (US);

Anthony Chiu, Richardson, TX (US);

Tarak A. Railkar, Plano, TX (US);

Assignee:

Qorvo US, Inc., Greensboro, NC (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 23/66 (2006.01); H01L 23/00 (2006.01); H01L 23/373 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/367 (2013.01); H01L 23/3731 (2013.01); H01L 23/3736 (2013.01); H01L 23/49827 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 23/66 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2223/6611 (2013.01); H01L 2223/6616 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48106 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/15153 (2013.01);
Abstract

The present disclosure relates to an air-cavity package, which includes a substrate, a base, and a semiconductor die. The substrate includes a substrate body, thermal vias extending through the substrate body, and a metal trace on a bottom side of the substrate body and separate from the thermal vias. The base includes a base body, a perimeter wall extending about a perimeter of the base body, and a signal via structure. Herein, the bottom side of the substrate body resides on the perimeter wall to form a cavity, and the signal via structure extends through the perimeter wall and is electrically coupled to the metal trace. The semiconductor die is mounted on the bottom side of the substrate body, exposed to the cavity, and electrically coupled to the metal trace. The thermal vias conduct heat generated from the semiconductor die toward a top side of the substrate body.


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