The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 08, 2019
Filed:
Mar. 04, 2015
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Shaojie Xu, San Jose, CA (US);
Yukit Tang, San Jose, CA (US);
Pao-Po Hou, Saratoga, CA (US);
Derek C. Tao, Fremont, CA (US);
Annie-Li-Keow Lum, San Jose, CA (US);
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A memory compiler includes a processor configured to perform a simulation of an operation of an input stage coupled to an input terminal of a memory circuit, wherein the simulation of the operation of the input stage is performed for various slew rate values at the input terminal to obtain corresponding extrinsic input timing delays. The processor is further configured to perform a simulation of an operation of an output stage coupled to an output terminal of the memory circuit, wherein the simulation of the operation of the output stage is performed for various capacitance loading values at the output terminal to obtain corresponding extrinsic output timing delays. The processor is further configured to perform a simulation of an operation of a section of the memory circuit between the input stage and the output stage to obtain an intrinsic timing delay. The processor is further configured to generate timing delays of the memory circuit based on the extrinsic input timing delays, the extrinsic output timing delays and the intrinsic timing delay.