The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2019

Filed:

Sep. 19, 2016
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Ruilong Xie, Niskayuna, NY (US);

Steven J. Bentley, Menands, NY (US);

Jody A. Fronheiser, Delmar, NY (US);

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/337 (2006.01); H01L 29/78 (2006.01); H01L 21/306 (2006.01); H01L 29/66 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7827 (2013.01); H01L 21/30604 (2013.01); H01L 29/401 (2013.01); H01L 29/41741 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66666 (2013.01);
Abstract

One illustrative method disclosed herein includes, among other things, defining a cavity in a plurality of layers of material positioned above a bottom source/drain (S/D) layer of semiconductor material, wherein a portion of the bottom source/drain (S/D) layer of semiconductor material is exposed at the bottom of the cavity, and performing at least one epi deposition process to form a vertically oriented channel semiconductor structure on the bottom source/drain (S/D) layer of semiconductor material and in the cavity and a top source/drain (S/D) layer of semiconductor material above the vertically oriented channel semiconductor structure. In this example, the method further includes removing at least one of the plurality of layers of material to thereby expose an outer perimeter surface of the vertically oriented channel semiconductor structure and forming a gate structure around the vertically oriented channel semiconductor structure.


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