The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2019

Filed:

Dec. 26, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Wen-Jia Hsieh, Changhua County, TW;

Hsin-Hung Chen, Tainan, TW;

Yi-Chun Lo, Hsinchu County, TW;

Jung-You Chen, Hsinchu County, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/08 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 29/165 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0847 (2013.01); H01L 21/0245 (2013.01); H01L 21/0262 (2013.01); H01L 21/02532 (2013.01); H01L 21/02576 (2013.01); H01L 21/823814 (2013.01); H01L 27/092 (2013.01); H01L 29/165 (2013.01); H01L 29/66628 (2013.01); H01L 29/66636 (2013.01); H01L 29/7834 (2013.01); H01L 29/7848 (2013.01); H01L 21/823807 (2013.01);
Abstract

A semiconductor device includes: a gate structure on a substrate; a raised source/drain region adjacent to the gate structure; a channel region under the gate structure; and a protection layer between the substrate and the raised source/drain region. The protection layer is interposed between the substrate and the raised source/drain region. An atom stacking arrangement of the protection layer is different from the substrate and the raised source/drain region.


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