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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10170471 B1

PDFFull Text
Date of Patent:
Jan. 01, 2019

Filed:

Oct. 13, 2016

Bulk fin formation with vertical fin sidewall profile

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Kangguo Cheng, Schenectady, NY (US);

Hong He, Schenectady, NY (US);

Sivananda K. Kanakasabapathy, Niskayuna, NY (US);

Chiahsun Tseng, Wynantskill, NY (US);

Yunpeng Yin, Niskayuna, NY (US);

Assignee:

International Business Machines Corporation, Armonk, NY (US);

Attorney:

Edward J. Wixted, III

Primary Examiner:

Jesse Y Miyoshi

Assistant Examiner:

John Lin

Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 27/088 (2006.01); H01L 21/84 (2006.01); H01L 21/762 (2006.01); H01L 21/311 (2006.01); H01L 29/66 (2006.01); H01L 21/308 (2006.01); H01L 21/3065 (2006.01); H01L 21/02 (2006.01); H01L 21/8234 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/02236 (2013.01); H01L 21/3065 (2013.01); H01L 21/3081 (2013.01); H01L 21/3086 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/76202 (2013.01); H01L 21/823431 (2013.01); H01L 21/845 (2013.01); H01L 27/1211 (2013.01); H01L 29/165 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 21/02255 (2013.01);
Abstract

A semiconductor device, having a heterogeneous silicon stack, wherein the heterogeneous silicon stack comprises at least a base layer, a doped silicon layer, and an undoped silicon layer. The semiconductor device further includes a plurality of silicon fins atop a doped silicon oxide fin layer and an undoped silicon oxide fin layer, wherein the plurality of silicon fins have a uniform width along the height of the plurality of silicon fins, and wherein the plurality of silicon fins have a plurality of hard mask caps.

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