The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 01, 2019
Filed:
Jun. 12, 2017
Globalfoundries Singapore Pte. Ltd., Singapore, SG;
Tsung-Che Tsai, Singapore, SG;
Manjunatha Govinda Prabhu, Clifton Park, NY (US);
Vaddagere Nagaraju Vasantha Kumar, Singapore, SG;
GLOBALFOUNDRIES SINGAPORE PTE. LTD., Singapore, SG;
Abstract
Methods to forming low trigger-voltage ESD protection circuit in FinFET IC devices and resulting devices. Embodiments include providing a substrate including a first-type well area in an ESD region; forming a base junction of the first-type along the perimeter of the ESD region; forming a shallow trench isolation (STI) region adjacent the base junction; forming alternate emitter and collector junctions of a second-type adjacent the STI region, parallel to and spaced from each other by parallel additional STI regions; forming at least one gate perpendicular to and over a collector junction; and forming a floating ESD nodes of the first-type in the collector junction adjacent one side of the at least one gate.