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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10170413 B1

PDFFull Text
Date of Patent:
Jan. 01, 2019

Filed:

Mar. 09, 2017

Semiconductor device having buried metal line and fabrication method of the same

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Tetsu Ohtou, Hsinchu, TW;

Yusuke Oniki, Hsinchu, TW;

Hidehiro Fujiwara, Hsinchu, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;

Attorney:

McClure, Qualey & Rodack, LLP

Primary Examiner:

Mark Prenty

Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 23/528 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5228 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 23/5286 (2013.01); H01L 23/5329 (2013.01); H01L 23/53257 (2013.01); H01L 27/0924 (2013.01); H01L 29/0649 (2013.01); H01L 29/66545 (2013.01);
Abstract

A device is disclosed that includes a memory bit cell, a first word line, a pair of metal islands and a pair of connection metal lines. The first word line is disposed in a first metal layer and is electrically coupled to the memory bit cell. The pair of metal islands are disposed in the first metal layer at opposite sides of the word line and are electrically coupled to a power supply. The pair of connection metal lines are disposed in a second metal layer and are configured to electrically couple the metal islands to the memory bit cell respectively.

Find Patent Forward Citations

Ohtou, Tetsu. (2019). Semiconductor device having buried metal line and fabrication method of the same (U.S. Patent No. 10170413). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10170413

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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