The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2019

Filed:

Feb. 20, 2018
Applicants:

United Microelectronics Corp., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian Province, CN;

Inventors:

Chieh-Te Chen, Kaohsiung, TW;

Feng-Yi Chang, Tainan, TW;

Fu-Che Lee, Taichung, TW;

Yi-Wang Zhan, Taichung, TW;

Assignees:

UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian Province, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/033 (2006.01); H01L 27/108 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 21/0338 (2013.01); H01L 21/0332 (2013.01); H01L 21/0335 (2013.01); H01L 21/0337 (2013.01); H01L 21/7687 (2013.01); H01L 21/76816 (2013.01); H01L 21/76843 (2013.01); H01L 27/10855 (2013.01);
Abstract

A method of forming a patterned structure is provided in the present invention. A hard mask layer is formed on a material layer before a first etching process and a second etching process for forming a first opening and a second opening partially overlapping with each other in the hard mask layer. The hard mask layer having the first opening and the second opening is then used in a third etching process performed to the material layer. A fourth etching process is performed to the hard mask layer and a dielectric layer disposed under the material layer after the third etching process. The material of the hard mask layer is identical to the material of the dielectric layer, and the fourth etching process may be used to remove the hard mask layer and form a trench in the dielectric layer accordingly.


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