The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2019

Filed:

Sep. 20, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Mahesh Natu, Sunnyvale, CA (US);

Thanunathan Rangarajan, Bangalore, IN;

Gautam Doshi, Bangalore, IN;

Shamanna M. Datta, Hillsboro, OR (US);

Baskaran Ganesan, Bangalore, IN;

Mohan J. Kumar, Aloha, OR (US);

Rajesh S. Parthasarathy, Hillsboro, OR (US);

Frank Binns, Portland, OR (US);

Rajesh Nagaraja Murthy, Bangalore, IN;

Robert C. Swanson, Olympia, WA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 9/30 (2018.01); G11C 7/10 (2006.01); G11C 11/406 (2006.01); G06F 13/24 (2006.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 13/24 (2013.01); G06F 9/30101 (2013.01); G06F 9/30189 (2013.01); G06F 9/461 (2013.01); G11C 7/1072 (2013.01); G11C 11/40615 (2013.01); G06F 9/3017 (2013.01); G06F 9/3851 (2013.01);
Abstract

In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.


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