The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Jun. 13, 2017
Applicants:

Kiseok Suh, Hwaseong-si, KR;

Byoungjae Bae, Hwaseong-si, KR;

Gwanhyeob Koh, Seoul, KR;

Yoonjong Song, Seoul, KR;

Kilho Lee, Busan, KR;

Inventors:

Kiseok Suh, Hwaseong-si, KR;

Byoungjae Bae, Hwaseong-si, KR;

Gwanhyeob Koh, Seoul, KR;

Yoonjong Song, Seoul, KR;

Kilho Lee, Busan, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 43/02 (2006.01); H01L 43/08 (2006.01); H01L 27/22 (2006.01);
U.S. Cl.
CPC ...
H01L 43/02 (2013.01); H01L 27/222 (2013.01); H01L 43/08 (2013.01);
Abstract

A first lower interconnection structure and a second lower interconnection structure are formed using a first design rule on a first region of a substrate and a second region of the substrate, respectively. A memory element is formed on the first lower interconnection structure. The memory element includes a bottom electrode, a magnetic tunnel junction and a top electrode stacked on each other. An upper conductive line and an upper interconnection line are formed using a second design rule larger than the first design rule on the first lower interconnection structure and the second lower interconnection structure, respectively. The first lower interconnection structure, the memory element and the upper conductive line are stacked on each other so that the memory element is interposed between the first lower interconnection structure and the upper conductive line.


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