The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

May. 09, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Hari V. Mallela, Poughquag, NY (US);

Reinaldo A. Vega, Mahopac, NY (US);

Rajasekhar Venigalla, Hopewell Junction, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 21/84 (2006.01); H01L 27/088 (2006.01); H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 21/306 (2006.01); H01L 27/108 (2006.01); H01L 27/12 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78642 (2013.01); H01L 21/28088 (2013.01); H01L 21/30604 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823842 (2013.01); H01L 21/823857 (2013.01); H01L 21/823878 (2013.01); H01L 21/823885 (2013.01); H01L 21/845 (2013.01); H01L 27/0886 (2013.01); H01L 27/092 (2013.01); H01L 27/0922 (2013.01); H01L 27/0924 (2013.01); H01L 29/0649 (2013.01); H01L 29/0653 (2013.01); H01L 29/41741 (2013.01); H01L 29/42356 (2013.01); H01L 29/42392 (2013.01); H01L 29/4966 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01); H01L 29/78618 (2013.01); H01L 29/78648 (2013.01); H01L 29/78696 (2013.01); H01L 27/10826 (2013.01); H01L 27/10879 (2013.01); H01L 27/1211 (2013.01); H01L 29/41791 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7855 (2013.01); H01L 2029/42388 (2013.01); H01L 2924/13067 (2013.01);
Abstract

A method of fabricating a vertical field effect transistor comprising that includes forming openings through a spacer material to provide fin structure openings to a first semiconductor material, and forming an inner spacer liner on sidewalls of the fin structure openings. A channel semiconductor material is epitaxially formed on a surface of the first semiconductor material filling at least a portion of the fin structure openings. The spacer material is recessed with an etch that is selective to the inner spacer liner to form a first spacer. The inner spacer liner is removed selectively to the channel semiconductor material. A gate structure on the channel semiconductor material, and a second semiconductor material is formed in contact with the channel semiconductor material.


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