The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Oct. 03, 2016
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

En-Chiuan Liou, Tainan, TW;

Chih-Wei Yang, Kaohsiung, TW;

Yu-Cheng Tung, Kaohsiung, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42376 (2013.01); H01L 21/28008 (2013.01); H01L 21/76834 (2013.01); H01L 21/76897 (2013.01); H01L 29/4232 (2013.01); H01L 29/4966 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 21/28088 (2013.01);
Abstract

A semiconductor device having metal gate includes a substrate, a metal gate formed on the substrate, a pair of spacers formed on sidewalls of the metal gate, a contact etch stop layer (CESL) covering the spacers, an insulating cap layer formed on the metal gate, the spacers and the CESL, and an ILD layer surrounding the metal gate, the spacers, the CESL and the insulating cap layer. The metal gate, the spacers and the CESL include a first width, and the insulating cap layer includes a second width. The second width is larger than the first width. And a bottom of the insulating cap layer concurrently contacts the metal gate, the spacers, the CESL, and the ILD layer.


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