The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Jul. 12, 2017
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yi-Jyun Huang, New Taipei, TW;

Tung-Heng Hsieh, Hsinchu County, TW;

Bao-Ru Young, Zhubei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/311 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41791 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/28247 (2013.01); H01L 21/31105 (2013.01); H01L 21/76895 (2013.01); H01L 21/76897 (2013.01); H01L 21/823431 (2013.01); H01L 21/823475 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/401 (2013.01); H01L 29/41783 (2013.01); H01L 29/66795 (2013.01); H01L 29/0653 (2013.01); H01L 29/0847 (2013.01); H01L 29/66545 (2013.01);
Abstract

A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact, a separator, a plug contacting the source/drain contact and a wiring contacting the plug. The fin structure protrudes from an isolation insulating layer and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact is disposed on the first source/drain region. The separator is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact are in contact with a same face of the separator.


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