The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Dec. 13, 2017
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Kuo-Chen Wang, New Taipei, TW;

Shih-Fan Kuan, Taoyuan, TW;

Lars Heineck, Hiroshima, JP;

Sanh Tang, Kuna, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/027 (2006.01); H01L 21/762 (2006.01); H01L 23/528 (2006.01); H01L 27/108 (2006.01); H01L 29/06 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10823 (2013.01); H01L 21/0273 (2013.01); H01L 21/31053 (2013.01); H01L 21/31144 (2013.01); H01L 21/76224 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/53257 (2013.01); H01L 23/53271 (2013.01); H01L 27/10811 (2013.01); H01L 27/10855 (2013.01); H01L 27/10885 (2013.01); H01L 27/10888 (2013.01); H01L 27/10891 (2013.01); H01L 29/0649 (2013.01);
Abstract

A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.


Find Patent Forward Citations

Loading…